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External Memory Expansion Port (Port A)
Table 2-5. Phase-Lock Loop Signals (Continued)
Signal Name
PINIT
Type
Input
State During
Reset
Input
Signal Description
PLL Initial —During assertion of RESET, the value of PINIT is written
into the PLL enable (PEN) bit of the PLL control (PCTL) register,
determining whether the PLL is enabled or disabled.
NMI
Input
Nonmaskable Interrupt —After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the
negative-edge-triggered NMI request internally synchronized to
CLKOUT.
2.5 External Memory Expansion Port (Port A)
Note:
When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant Port A signals: A[0–17], D[0–23],
AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.
2.5.1 External Address Bus
Table 2-6. External Address Bus Signals
Signal Name
A[0–17]
Type
Output
State During
Reset
Tri-stated
Signal Description
Address Bus —When the DSP is the bus master, A[0–17] are
active-high outputs that specify the address for external program
and data memory accesses. Otherwise, the signals are
tri-stated. To minimize power dissipation, A[0–17] do not change
state when external memory spaces are not being accessed.
2.5.2 External Data Bus
Table 2-7. External Data Bus Signals
Signal Name
D[0–23]
Type
Input/ Output
State During
Reset
Tri-stated
Signal Description
Data Bus —When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[0–23] are tri-stated. These lines have
weak keepers to maintain the last state even if all drivers are
tri-stated.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
2-5
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